An LDO is a linear voltage regulator, and is mainly configured to provide a stable voltage source for a circuit. A main problem encountered in LDO design is frequency compensation of an LDO loop. Good frequency compensation may stabilize the LDO loop, increase a transient response speed of the LDO loop, and reduce static power consumption of the LDO loop.
In the prior art, a frequency compensation solution of an LDO is: adopting current Miller compensation. FIG. 1 is a schematic principle diagram of an LDO loop adopting current Miller compensation. A triangle symbol in the diagram represents a transconductance stage. The transconductance stage is a circuit that converts a voltage into a current, and is represented by gm. A negative sign in front of the gm indicates that a current output by the transconductance stage decreases as an input voltage increases. No negative sign in front of the gm indicates that the current output by the transconductance stage increases as the input voltage increases. In the diagram, r represents an equivalent resistor of a circuit node, and c represents an equivalent capacitor of the circuit node.
FIG. 2 shows an implantation manner of a specific circuit of the principle diagram shown in FIG. 1. An LDO circuit shown in FIG. 2 includes an operational amplifier circuit, an output power tube MP, a reference voltage VBG, two voltage divider resistors R1 and R2, and an external compensation capacitor CL, where Cpar is a parasitic capacitor of a Positive Channel Metal Oxide Semiconductor (PMOS) tube P8. RL represents an external load, Vin is an input voltage, and Vout is an output voltage.
An LDO circuit with an open loop structure shown in FIG. 3 is obtained when the R1 and R2 in FIG. 2 are disconnected. In the case that an output current is smaller than a set value (for example, 1 A), the LDO circuit with the open loop structure shown in FIG. 3 has the following two dominant poles:
            p      3        =                  -        1                              r          01                *                  C          par                                        p        4            =                        -          1                                      r            02                    *                      C            L                                ,  
where r01 represents an output resistance of an N1 point, r02 represents impedance obtained after an output resistance and a load resistance of the Pmos are connected in parallel, and Cpar represents an equivalent parasitic capacitance at the N1 point.
In the implantation of the present invention, the inventor finds that the frequency compensation solution of the LDO in the prior art has at least the following problems:
In the case that a small current is output, if a value of the r01 is larger, the pole P3 is located at a lower frequency, which affects the stability of the LDO loop. If the value of the r01 is smaller, although the pole P3 is located at a higher frequency, the stability of the LDO loop is desirable. However, the value of the r01 is smaller, which causes that an operational amplifier gain of the LDO loop is smaller in the case that a large current is output, so that performances of the LDO loop, such as load regulation, output voltage precision, and power supply noise suppression are deteriorated.